Description:
In modern microprocessors and systems-on-a-chip, the embedded memory system plays a key role in determining the design?s overall performance, power, area, reliability, and yield. As fabrication process technologies scale into the deep nanometer regime, increasing device variability poses particular difficulties for memory design due to the large number of variation-sensitive near minimum-sized devices in the cell arrays which often must achieve working circuits out beyond six sigma of variation to meet design targets at economically acceptable yields. Furthermore, as scaling progresses, soft errors in the memory system will also increase in frequency and scope, and single error events are more likely to cause large-scale multi-bit errors. Researchers have developed a number of variation- and soft error-tolerant techniques to mitigate parametric yield loss, performance loss, and information loss, but these techniques incur extremely high VLSI overheads.
Speaker(s):
Jangwoo Kim, PhD candidate, Computer Architecture Lab, Carnegie Mellon University
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