Description:
In this Microsoft Research video, Jayaram Mudigonda, post doctoral fellow at the University of Texas at Austin, discusses NP architecture that achieves versatility through malleability. In order to achieve versatility, NP architectures (and multi-core, multi-threaded architectures in general) must allow chip resources to be traded off dynamically between the two main mechanisms to mitigating the memory access overhead: data caching and hardware multithreading. Mudigonda presents a novel architecture that achieves this malleability by demonstrating that his team’s malleable processor, designed with the same chip area as Intel's IXP2800, can improve, across all the deployments considered, throughput by an average of 98 percent as compared to IXP2800. Further, in about one-third of the deployments, throughput improvement is as large as 300 percent. Learn about why this particular malleable NP architecture is substantially easier to program than today's commercial network processors.
Speaker(s):
Jayaram Mudigonda, Ph.D., post doctoral fellow, Computer Sciences, University of Texas at Austin
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